While reducing the dimensions of one element (downscaling) has been necessary to increase the storage capacity in semiconductor memory devices (memory), multi-bit storage technology in which two or more bits of information are stored in one memory cell is also becoming necessary to store more information.
Improvements to photolithography technology and technology to form memory cells in three-dimensional structures are being considered to downscale memory cells.
The inventors of the application have proposed collectively patterned three-dimensionally stacked memory cells that realize a three-dimensional structure using few processes (for example, refer to JP-A 2007-320215 (Kokai)). According to this method, it is possible to suppress cost increases because it is possible to form a stacked memory collectively regardless of the number of stacks.
As such downscaling of memory cells progresses, interference between adjacent cells greatly affects the reliability of the data. Particularly in the case where multi-bit information is stored, the reliability is affected when the thresholds of memory cell transistors corresponding to the multi-bit information programmed to the memory cells fluctuate due to the information of adjacent cells; and the data retention characteristics also may be affected.